How to migrate PCB design from 16 GT/s PCIe 4.0 to 32 GT/s PCIe 5.0?

Planning to migrate PCB design from 16 GT/s PCIe 4.0 to 32 GT/s PCIe 5.0? The analysis of links running at 16 or 32 GT/s (or Gbps) signals must be done with 3D EM analysis and may require optimization. Simulation-based ERC analysis in Simbeor SI Compliance Analyzer is used in this demo for a preliminary evaluation of the link impedance, reference discontinuities and potential aggressors (see it with higher resolution at ). The link looked OK at 16 Gbps, but not so much at 32 Gbps. Further 3D SI analysis in Simbeor with 3D EM models for vias, AC coupling caps and BGA and connector pads reveals that the link is not compliant with the specs - too much reflections at higher frequencies. It took literally a couple of clicks, to get from ERC to 3D EM modeling of the complete link - ports, boundary conditions are all set automatically. You can run such analysis either on a laptop or accelerate with the distributed computing in a AWS cloud. What would be done next? Optimize vias (they are too inductive), make cutouts below AC coupling caps and pads (they are too capacitive) - all that can be done in Simbeor software as demonstrated in multiple demo-videos at Finally, modify link layout and re-run the analysis in Simbeor. As soon as each link in a bus passes the reflection and insertion loss tests, proceed with the whole bus analysis, to evaluate the crosstalk between traces and vias... #simbeor #electromagnetics #signal_integrity