Gigabit Ethernet + FPGA/SoC Bring-Up (Zynq Part 4) - Phil’s Lab #99

Gigabit Ethernet PHY (physical layer) and AMD/Xilinx Zynq SoC (System-on-Chip) configuration. Schematic and PCB layout/routing overview, RGMII/MDIO/MDI signals, Vivado and Vitis configuration, fixing driver bugs, example TCP bandwidth performance application, and test. PCBs by PCBWay [SUPPORT] Free trial of Altium Designer: Patreon: Mixed-signal hardware design course: Advanced Hardware Design Course Survey: [GIT] [LINKS] Instagram: iPerf: PHY datasheet: [TIMESTAMPS] 00:00 Introduction & Previous Videos 01:05 PCBWay 01:45 Altium Designer Free Trial 02:11 Hardware Overview 03:36 Schematic 05:35 PCB Layout & Routing 06:37 Physical Layer (PHY) 07:14 Vivado Ethernet Set-Up 11:10 Vitis TCP Performance Server Example 12:03 Driver Fix #1 - Autonegotiation Off 13:02 Driver Fix #2 - Link Up/Down Bug 16:26 Hardware Connection 16:42 COM Port Set-Up & Programming 18:14 iPerf Tool 18:37 Bandwidth Performance Test 21:09 Summary 22:08 Outro